Analog/Mixed-Signal Layout Engineer

Link Consulting Services

  • São Paulo - SP
  • Permanente
  • Período integral
  • Há 6 dias
We are looking for 10 technical and non-technical profiles. This will be a hybrid position in the Sao Paulo Metropolitan area.As a key member of the IC design team, you will be responsible for layout design and physical implementation of complex analog, mixed-signal, and RF circuits. You will contribute to the development of high-speed SerDes PHYs, DDR PHYs, PLLs, ADCs/DACs, and power management blocks. Your expertise in layout floor-planning, hierarchical assembly, and advanced CMOS process effects will ensure signal integrity, low power consumption, and long-term reliability of silicon.Key Responsibilities:
  • Design and implement layouts for analog, RF, memory, and mixed-signal circuits including SerDes, PHYs, PLLs, DDR interfaces, ADCs/DACs, and LDOs.
  • Perform layout floor-planning, device placement, and routing to optimize performance, power, and area (PPA).
  • Apply advanced layout techniques to minimize parasitics, IR drop, crosstalk, EM, ESD, and latch-up risks.
  • Ensure robust designs through device matching, shielding, isolation, and guard ring/DNW strategies.
  • Collaborate closely with circuit designers, verification engineers, and process technologists to validate design intent.
  • Address layout-dependent effects (LOD, WPE, stress effects) and implement mitigation strategies.
  • Support tape-out activities including design rule checks (DRC), LVS, and parasitic extraction (PEX).
  • Stay updated with emerging SerDes PHY trends (PIPE interface, adaptive DSP, AI-driven equalization) and integrate best practices into design.
Required Knowledge & Skills:
  • Proven expertise in analog/mixed-signal, RF, memory, and custom digital layout.
  • Strong understanding of SerDes PHY design principles, PCIe PIPE interface, and high-speed interconnects.
  • Proficiency in layout methodologies for matching, parasitic minimization, and high-frequency routing.
  • Experience with guard rings, DNW, PN junctions, ESD, latch-up prevention, and reliability considerations.
  • Familiarity with advanced process effects (LOD, WPE, STI stress).
  • Basic circuit design understanding to collaborate effectively with circuit engineers.
  • Experience using industry-standard EDA tools (e.g., Cadence Virtuoso, Synopsys, Mentor Graphics).
Preferred Qualifications:
  • 5+ years of experience in IC layout design (analog, RF, or SerDes PHY).
  • Experience in sub-7nm CMOS or FinFET processes.
  • Knowledge of high-speed interconnect protocols (PCIe, Ethernet, DDR).
  • Familiarity with AI-driven design optimization is a plus.

Link Consulting Services